The circuit density of dynamic semiconductor memory storage devices continues to increase at a fairly constant rate. One method of providing such increase in capacity is the advent of the stacked capacitor dynamic access memory (DRAM). To most efficiently utilize this increase in memory capacity, that a stacked capacitor DRAM provides, requires decreasing the access time. However, a major problem with the stacked DRAMs is caused by stack height. As the stack height increases, the digit-line which is placed perpendicular to the word-line and so goes over the word-line topography increases in length, with an attendant increase in its resistance. As DRAM digit-line resistance is a critical parameter that determines the speed performance of the device, various methods are being tried in order to reduce such resistance.
A paper submitted by Y. Kawamoto et al., entitled "A 1.28.mu.m.sup.2 Bit-Line Shielded Memory Cell Technology for 64Mb DRAMs", Symposium on VLSI Technology, p. 13, 1990, herein incorporated by reference, discusses a method of fabricating a stacked DRAM having a reduced resistance bit-line.
The planarized bit-line (so referred to in the article) process requires a thick Polysilicon film deposited on the surface to fill the spacing between the word-lines. When the planarization is carried out using an insulator such as SiOz, it is impossible to open the bit-line contact-hole self- aligned to the word-line. Accordingly, the Polysilicon is adapted to planarize the word-line steps.
Next, WSi.sub.x film is deposited over the planarized Polysilicon surface after the Polysilicon is etched back to a remaining thickness of less than 100 nm above the word-line. This planarized bit-line produces a DRAM with low-power dissipation.
The Polycide bit-line used in this process consists of the WSi.sub.x and Polysilicon double layers instead of other low-resistance materials because high temperature treatment is necessary to fabricate the storage capacitor after bit-line wiring. Accordingly, this "BRIDGE ALL" method while resulting in a lower bit-line resistance adds additional process complexity to the manufacture of the stacked capacitor DRAM.
Additional use of the planarized or BRIDGE ALL method of producing a bit-line is shown in a paper submitted by T. Kaga et al., entitled "Crown-Shaped Stacked-Capacitor Cell for 1.5-V Operation 64-Mb DRAMs", IEEE Transactions On Electron Devices, volume 38, number 2, Feb. 1991, pages 255-260. In this paper, and referring in particular to FIG. 8, on page 258, the Bridge All method, is again described and compared with a conventional nonplanarized bit-line. Again, use of the Bridge All method increases manufacturing process complexity. For instance, if the word-line gaps are chosen small so that the digit-line Polysilicon deposition (Poly2) bridges them all, a small word-line gap at buried contact 2 (BC2) implies a small BC2 contact region. This makes the BC2 contact process less production-worthy. If, however, the bridging is alternatively achieved by depositing very thick Poly2, the Poly2 etch-back becomes a critical step, increasing the manufacturing complexity of the device.
Another method, the "GAP ALL" method has been proposed wherein the digit-line is deposited so as to follow the contours of all gaps between word-lines. In both the GAP ALL method and the above-mentioned BRIDGE ALL method, we have discovered that there is a critical gap between word-lines where the digit-line resistance rises abruptly as the digit-line follows the contours or gap between the word-lines. At the critical gap spacing, the resistance of the digit-line rises an order of magnitude or greater. Factors in determining the critical gap include the Poly thickness and the word-line Spacer thickness.
The present invention produces a reduced resistance digit-line by utilizing a bridging method where the gap between word-lines is less than the above-described critical gap and uses a gaping method where the distance between word-lines is larger or greater than the critical gap.